In general, all electronic equipment generates electromagnetic noise that could disturb its own operation or the operation of equipment nearby it.
The proliferation of equipment based on electronics and radio systems required the definition of regulations in terms of ElectroMagnetic Compatibility (EMC).
According to one commonly accepted definition, electromagnetic compatibility means the capability of equipment or a system to operate satisfactorily within its electromagnetic environment without itself producing any intolerable electromagnetic disturbances for all equipment located in this environment.
Therefore, the electromagnetic environment has become an essential parameter to be taken into account in the design of any electronic equipment.
At the moment, more and more integrated circuits are equipped with tens or even hundreds of very fast output peripherals.
However, these peripherals generate high noise levels that can disturb the operation of nearby systems. For example, this is a problem particularly in the field of onboard electronics.
Remember that the main source of conducted and/or radiated electromagnetic disturbances is “di/dt” current peaks and “dv/dt” voltage peaks generated each time that these peripherals are switched.
Identical elements or signals are denoted by the same alphanumeric reference on all the figures in this document.
The electrical diagram for a conventional output buffer reference 100 (also subsequently referred to as first classical buffer or buffer without anti short-circuit and without EMC optimization), is also shown with reference to FIG. 1.
In order to simplify the description we will limit the remainder of the description to the special case of integrated circuits operating at power supply voltages of 0V and 5V. Those skilled in the art will be able to extend this information without any difficulty to any type of voltage that will power an onboard electronic circuit.
The output buffer 100 receives a first input signal S1 on a first input 1 and a second input signal S2 on a second input 2, and an output signal SOUT at the output 3.
This output buffer 100 comprises a first control stage 34 comprising first high and low inverters 301 and 302, and a first switching stage 35 including first high and low switching means 303 and 304.
More precisely, the first high inverter 301 receives the first input signal S1 on an input 341 and it outputs a first control signal SCOM1 to a first mid-point A. This high inverter 301 comprises a transistor TP1, the source SP1 of which is connected to the power supply VCC of the circuit (also called the high logical level in the remainder of this description), and the drain DP1 of which is connected to the first mid-point A, and a transistor TN1, the source SN1 of which is connected to the reference potential VSS (also called the low logical level in the remainder of the description), and the drain DN1 of which is connected to the drain DP1 of the transistor TP1. The transistors TP1 and TN1 receive the first input signal S1 on their gates GP 1 and GN1.
Thus, when the first input signal S1 is approximately equal to the reference potential VSS, namely 0V, the transistor TP1 is made conducting and the transistor TN1 is blocked. The high inverter 301 then outputs a first control signal SCOM1 to the first mid-point A, that is approximately equal to the power supply VCC, namely 5V.
Conversely, when the first input signal S1 is approximately equal to the power supply VCC, namely 5V, the transistor TN1 is made conducting and the transistor TP1 is blocked. The high inverter 301 then outputs a first control signal SCOM1 to the first mid-point A that is approximately equal to the reference potential VSS, namely 0V.
The first low inverter 302 receives the second input signal S2 on an input 342 and it outputs a second control signal SCOM2 to a second mid-point B. This low inverter 302 comprises a transistor TP2, the source SP2 of which is connected to the power supply VCC and the drain DP2 of which is connected to the second mid-point B, and a transistor TN2, the source SN2 of which is connected to the reference potential VSS and the drain DN2 of which is connected to the drain DP2 of the transistor TP2. The transistors TP2 and TN2 receive the second input signal S2 on their gates GP2 and GN2.
Thus, when the second input signal S2 is approximately equal to the reference potential VSS, namely 0V, the transistor TP2 is made conducting and the transistor TN2 is blocked. The low inverter 302 then outputs a second control signal SCOM2 to the second mid-point B, that is approximately equal to the power supply VCC, namely 5V.
Conversely, when the second input signal S2 is approximately equal to the power supply VCC, namely 5V, the transistor TN2 is made conducting and the transistor TP2 is blocked. The low inverter 302 then outputs a second control signal SCOM2 to the second mid-point B that is approximately equal to the reference potential VSS, namely 0V.
The first high and low switching means 303 and 304 comprise a transistor TP3 and a transistor TN3 respectively.
The transistor TP3, the source SP3 of which is connected to the power supply VCC and the drain DP3 of which is connected to the output 3, forms a switch controlled by the first control signal SCOM1 (applied to the gate DP3).
The transistor TN3, the source SN3 of which is connected to the reference potential VSS and the drain DN3 of which is connected to the drain DP3 of the transistor TP3, forms a switch controlled by the second control signal SCOM2 (applied to the gate GN3).
The following describes operation of the output buffer 100 according to prior art for four combinations of input signals S1 and S2, with reference to FIG. 1.
For the first combination, the first and second input signals S1 and S2 are approximately equal to the reference potential VSS, namely 0V. The first and second control signals SCOM1 (output at mid-point A) and SCOM2 (output at mid-point B) are then approximately equal to the power supply VCC, namely 5V. The transistor TP3, the gate GP3 of which receives the first control signal SCOM1, is therefore put into a blocked state (switch open). On the other hand, the transistor TN3, the gate GN3 of which receives the second control signal SCOM2, is put into a conducting state (switch closed) in which it carries the reference potential VSS to the output 3.
For the second combination, the first and second input signals S1 and S2 are approximately equal to the power supply VCC, namely 5V. The first and second control signals SCOM1 and SCOM2 are then approximately equal to the reference potential VSS, namely 0V. Therefore the transistor TN3, the gate GN3 of which receives the second control signal SCOM2, is put into a blocked state (switch open). On the other hand, the transistor TP3, the gate GP3 of which receives the first control signal SCOM1, is put into a conducting state (switch closed) in which it carries the power supply VCC to the output 3.
For the third combination, the first input signal S1 is approximately equal to the reference potential VSS, namely 0V, and the second input signal S2 is approximately equal to the power supply VCC, namely 5V. The first control signal SCOM1 is then approximately equal to the power supply VCC and the second control signal SCOM2 is approximately equal to the reference potential VSS. Therefore the transistors TP3 and TN3 are both in the blocked state. Thus, for this combination, there is concomitant blocking of the switching means (TP3 and TN3 blocked). In this case, the result is high impedance output.
For the fourth combination, the first input signal S1 is approximately equal to the power supply VCC, namely 5V, and the second input signal S2 is approximately equal to the reference potential VSS, namely 0V. The first control signal SCOM1 is then approximately equal to the reference potential VSS and the second control signal SCOM2 is approximately equal to the power supply VCC. Therefore the transistors TP3 and TN3 are both in a conducting state.
Thus, for this combination, it is seen that prior art introduces a short circuit between the power supply VCC and the reference potential VSS.
Another major disadvantage of this first known technique lies in the fact that it has potential reliability problems by electromigration, particularly in the case of very fast buffers.
Furthermore, this first classical buffer has a large “di/dt” current variation in output transistors TP3 and TN3; which results in generation of high electromagnetic noise.
The traditional way of overcoming this short circuit problem is to introduce memory points into the above mentioned output buffer 100. As illustrated in FIG. 2, in the classical output buffer reference 200 (also referred to as the second classical buffer or buffer with anti short-circuit and without EMC optimization in the following description), the high memory point C is obtained by feedback from the first high switching means 303 to the first low inverter 302 (in other words the gate GP3 of transistor TP3 is connected to the source SP2 of transistor TP2) and the low memory point D is obtained by feedback from the first low switching means 304 to the first high inverter 301 (in other words the gate GN3 of transistor TN3 is connected to the source SN1 of transistor TN1). This double feedback imposes a stable voltage (or a stable logical level) on high and low memory points C and D, so as to delete indeterminate logical states of the first high and low switching means 303 and 304. This solution prevents putting switching means into conduction and prevents short circuit and the risk of failure by electromigration.
In the case of the fourth combination (S1 equal to VCC and S2 equal to VSS), transistors TN1 and TP2 are put into a conducting state and transistors TP1 and TN2 are put into a blocked state; consequently, the gates GP3 and GN3 of transistors TP3 and TN3 are connected together and are floating with respect to the reference potential VSS and the power supply VCC. Thus, for this combination, the double feedback creates a capacitive effect that keeps the SCOM1 and SCOM2 control signals (applied to gates GP3 and GN3 respectively) at their previous logical levels.
Although this solution according to prior art represented important progress in the mechanism to eliminate short circuits, the second known technique does have the disadvantages of having a fairly high <<di/dt>> (i.e. current variation) and a corresponding electromagnetic disturbance. The double feedback of the second classical buffer 200 provides the means of adjusting the slew rate of the output signal in response to a rising or falling front applied to the circuit input. In other words, this double feedback introduces an additional charge capacitance that slightly slows down control of the first high and low switching means 303 and 304 of the buffer 200. However, this control is incapable of reducing so-called “di/dt” output current peaks from the circuit sufficiently to obtain an acceptable generated noise.